DK-DEV-5AGXB3N/ES【PDF 21/39 页】ARRIA V DEVELOPMENT KIT

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AV-51001

2013.12.26

Clock Networks and PLL Clock Sources

Memory Block

M20K

M10K

Depth (bits)

512

16K

256

512

Programmable Width

x40

x20

x10

x40 or x32

x20 or x16

x10 or x8

x5 or x4

Clock Networks and PLL Clock Sources

Arria V devices have 16 global clock networks capable of up to 650 MHz operation. The clock network

architecture is based on Altera's global, quadrant, and peripheral clock structure. This clock structure is

supported by dedicated clock input pins and fractional PLLs.

Note: To reduce power consumption, the Quartus II software identifies all unused sections of the clock

network and powers them down.

PLL Features

The PLLs in the Arria V devices support the following features:

Frequency synthesis

On-chip clock deskew

Jitter attenuation

Counter reconfiguration

Programmable output clock duty cycles

PLL cascading

Reference clock switchover

Programmable bandwidth

Dynamic phase shift

Zero delay buffers

Fractional PLL

In addition to integer PLLs, the Arria V devices use a fractional PLL architecture. The devices have up to 16

PLLs, each with 18 output counters. One fractional PLL can use up to 18 output counters and two adjacent

Arria V Device Overview

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